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enpirion ? power datasheet ep53a8lqa/hqa 1a powersoc voltage mode synchronous pwm buck with integrated inductor description the ep5 3a8lqa and EP53A8HQA are 1 a powersoc s that are aec - q100 qualified for automotive applications. the device integrates mosfet switches, control, compensation, and the inductor in an advanced 3mm x 3mm qfn package. integrated inductor ensures the complete power solution is fully characterized with the inductor carefully matched to the silicon and compensation network. it enables a tiny solution footprint, low output ripp le, low part - count, and high reliability, while maintaining high efficiency. the complete solution can be implemented in as little as 2 7 mm 2 and operate from - 40c to 105c ambient temperature range. the ep53a8x qa uses a 3 - pin vid to easily select the outpu t voltage setting. output voltage settings are available in 2 optimized ranges providing coverage for typical v out settings. the vid pins can be changed on the fly for fast dynamic voltage scaling. ep53a8l qa further has the option to use an external voltage divider. features ? integrated inductor technology ? - 40c to + 105c ambient temperature range ? aec - q100 qualified for automotive applications ? 3mm x 3mm x 1.1mm qfn p ackage ? total solution footprint ~ 27 mm 2 ? low v out r ipple for io c ompatibility ? high e fficiency, up to 94% ? v out range 0.6v to v in ? 0.5v ? 1a continuous output c urrent ? 5 mhz switching f requency ? 3- pin vid for glitch free voltage s caling ? short circuit and over current p rotection ? uvlo and thermal p rotection ? ic l evel reliability in a powersoc s olution applications ? automotive applications aec - q100 requirement ? portable wireless and rf applications ? wireless broad b and data c ards ? solid state storage applications ? noise and space sensitive a pplications v out v in 10f 0805 x7r 4.7f 0603 x7r vout pvin avin pgnd agnd vsense ep53a8xqa 100? vfb vs0 vs1 vs2 enable figure 1 . simplified applications circuit figure 2. highest efficiency in smallest solution size 40 45 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 efficiency (%) output current (a) efficiency vs. i out (v in = 3.3v) vout = 2.5v odto v = 3.3v 27mm 2 www.altera.com/enpirion 10366 october 1, 2014 rev a
ep53a8lqa/ep53a8hq a ordering information part number package markings t a (c) package description e p5 3 a 8 l qa bj xx - 40 to + 105 16 - pin ( 3 mm x 3 mm x 1. 1 mm) qfn EP53A8HQA b m xx - 40 to +105 16 - pin (3mm x 3mm x 1.1mm) qfn evb - e p53a8x qa qfn evaluation board packing and marking information : www.altera.com/support/reliability/packing/rel - packing - and- marking.html pin assignments (top view) figure 3. ep53a8l qa pin out diagram (top view) figure 4. ep53a8h qa pin out diagram (top view) note a : nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. note b : white ?dot? on top left is pin 1 indicator on top of the device package . pin description pin name function pin n am e function 1, 15, 16 nc(sw) no connect ? these pins are internally connected to the common switching node of the internal mosfets. nc (sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage to the device. 2,3 pgnd power ground. connect this pin to the ground electrode of the input and output filter capacitors. 4 vfb ep53a8l qa : feedback pin for external divider option. ep53a8h qa : no connect 5 vsense sense pin for preset output voltages. refer to application section for proper configuration. 6 agnd analog ground. this is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider 7, 8 vout regulated output voltage. refer to application section for proper layout and decoupling. nc(sw) pgnd vfb vsense agnd 1 2 3 4 5 6 pvin avin enable vs0 vs2 14 13 12 11 10 9 nc(sw) nc(sw) 16 15 pgnd vout vout vs1 7 8 nc(sw) pgnd nc vsense agnd 1 2 3 4 5 6 pvin avin enable vs0 vs2 14 13 12 11 10 9 nc(sw) nc(sw) 16 15 pgnd vout vout vs1 7 8 www.altera.com/enpirion , page 2 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa pin name function 9, 10, 11 vs2, vs1, vs0 output voltage select. vs2 = pin 9, vs1 = pin 10, vs0 = pin 11. ep53a8l qa : selects one of seven preset output voltages or an external resistor divider. ep53a8h qa : selects one of eight preset output voltages. (refer to section on output voltage select for more details.) 12 enable output enable. enable = logic high; disable = logic low 13 avin input power supply for the controller circuitry. connect to pvin through a 100 ohm resistor. 14 pvin input voltage for the mosfet switches. absolute maximum ratings caution : absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute maximum ratings may impair device life. exposure to absolute maximum rated conditions for extended periods may affect device reliability. param eter sym bol min m ax units input supply voltage v in - 0.3 6.0 v voltages on: enable, v sense , v so ? v s2 - 0.3 v in + 0.3 v voltages on: v fb (ep53a8l qa ) - 0.3 2.7 v maximum operating junction temperature t j- abs 150 c storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020c 260 c esd rating (based on human body mode) 2000 v recommended operating conditions param eter sym bol min m ax units input voltage range v in 2.4 5.5 v operating ambient temperature t a - 40 +105 c operating junction temperature t j - 40 +125 c thermal characteristics param eter sym bol typ units thermal resistance: junction to ambient ? 0 lfm ( note 1 ) ja 80 c/w thermal overload trip point t j- tp +155 c thermal overload trip point hysteresis 25 c note 1 : based on a four layer copper board and proper thermal design per jedec eij/jesd51 standards . electrical characteristics note: v in =3 .6 v , minimum and m aximum values are over operating ambient temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ m ax units operating input voltage v in 2.4 5.5 v under voltage lock - out ? v in rising v uvlo_r 2.0 v under voltage lock - out ? v in falling v uvlo_f 1.9 v www.altera.com/enpirion , page 3 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa parameter symbol test conditions min typ m ax units drop out resistance r do input to output resistance 350 500 m? ? v out t a = 25 c, v in = 3.6v; i load = 100ma ; 0.8v v out 3.3v -2 +2 % feedback pin voltage initial accuracy v fb t a = 25 c, v in = 3.6v; i load = 100ma ; 0.8v v 3.3v ? v out_line 2.4v v in 5.5v ; load = 0a 0.03 %/v load regulation ? 0a i ? v out_templ - 40 c t a +105 c 30 ppm/ c output current range i out subject to de - rating 0 1000 ma shut - down current i sd enable = low 0.75 a ocp threshold i lim 2.4v v 5.5v 0.6v v out 3.3v 1.25 1.4 a vs0 - vs2, pin logic low v vslo 0.0 0.3 v vs0 - vs2, pin logic high v vshi 1.4 v in v vs0 - vs2, pin input current i vsx note 1 <100 na enable pin logic low v enlo 0.3 v enable pin logic high v enhi 1.4 v enable pin current i enable note 1 <100 na feedback pin input current i fb note 1 <100 na operating frequency f osc 5 mhz pok lower threshold pok lt output voltage as a fraction of expected output voltage 90 % pok output low voltage v pokl with 4ma current sink into pok 0.4 v pok output hi voltage v pokh 2.5 v v 6.6 soft start operation www.altera.com/enpirion , page 4 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa parameter symbol test conditions min typ m ax units soft start slew rate ? v ss ep53a8h qa (vid only) ep53a8l qa (vid only) 8 4 v/ms soft start rise time ? t ss ep53a8l qa (vfb mode); note 2 170 225 280 s note 1 : parameter guaranteed by design and characterization. note 2: measured from when v in v uvlo_r & enable pin crosses its logic high threshold. www.altera.com/enpirion , page 5 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa typical performance curves 40 45 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 efficiency (%) output current (a) efficiency vs. i out (v in = 3.3v) vout = 2.5v vout = 1.8v vout = 1.5v vout = 1.2v vout = 1.0v odto v = 3.3v 35 0 5 50 55 0 5 0 5 80 85 0 5 0 0.1 0.2 0.3 0. 0.5 0. 0. 0.8 0. 1 outut ut a efficiency vs. i out (v in = 5.0v) vout = 3.3v vout = 2.5v vout = 1.8v vout = 1.5v vout = 1.2v vout = 1.0v odto v = 5v 0.80 0.85 0.0 0.5 1.000 1.005 1.010 1.015 1.020 0 0.1 0.2 0.3 0. 0.5 0. 0. 0.8 0. 1 outut volta v outut ut a output voltage vs. output current vin = 5.0v vin = 3.3v conditions v out = 1.0v 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output voltage (v) output current (a) output voltage vs. output current vin = 5.0v vin = 3.3v conditions v out = 1.2v 1.480 1.485 1.490 1.495 1.500 1.505 1.510 1.515 1.520 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output voltage (v) output current (a) output voltage vs. output current vin = 5.0v vin = 3.3v conditions v out = 1.5v 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output voltage (v) output current (a) output voltage vs. output current vin = 5.0v vin = 3.3v conditions v out = 1.8v www.altera.com/enpirion , page 6 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa typical performance c urves (continued) 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output voltage (v) output current (a) output voltage vs. output current vin = 5.0v vin = 3.3v conditions v out = 2.5v 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output voltage (v) output current (a) output voltage vs. output current vin = 5.0v conditions v out = 3.3v 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 2.5 3 3.5 4 4.5 5 5.5 output voltage (v) input voltage (v) output voltage vs. input voltage load = 0a load = 1a odto v outo = 1.0v 1.180 1.185 1.10 1.15 1.200 1.205 1.210 1.215 1.220 2.5 3 3.5 .5 5 5.5 outut volta v ut volta v output voltage vs. input voltage load = 0a load = 1a odto v outo = 1.2v 1.80 1.85 1.0 1.5 1.500 1.505 1.510 1.515 1.520 2.5 3 3.5 .5 5 5.5 outut volta v ut volta v output voltage vs. input voltage load = 0a load = 1a odto v outo = 1.5v 1.80 1.85 1.0 1.5 1.800 1.805 1.810 1.815 1.820 2.5 3 3.5 .5 5 5.5 outut volta v ut volta v output voltage vs. input voltage load = 0a load = 1a odto v outo = 1.8v .. 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa typical performance curves (continued) 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 3 3.5 4 4.5 5 5.5 output voltage (v) input voltage (v) output voltage vs. input voltage load = 0a load = 1a odto v outo = 2.5v 3.280 3.285 3.20 3.25 3.300 3.305 3.310 3.315 3.320 5 5.1 5.2 5.3 5. 5.5 outut volta v ut volta v output voltage vs. input voltage load = 0a load = 1a odto v outo = 3.3v 0.80 0.0 1.000 1.010 1.020 1.030 50 30 10 10 30 50 0 0 110 outut volta v at tatu output voltage vs. temperature load = 0a load = 1a conditions v in = 3.3v v out_nom = 1.0v 0.980 0.990 1.000 1.010 1.020 1.030 -50 -30 -10 10 30 50 70 90 110 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a conditions v in = 5.0v v out_nom = 1.0v 3.280 3.290 3.300 3.310 3.320 3.330 3.340 3.350 -50 -30 -10 10 30 50 70 90 110 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a conditions v in = 5.0v v out_nom = 3.3v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 55 60 65 70 75 80 85 90 95 100 105 maximum output current (a) ambient temperature ( c) output current de - rating vout = 1.0v vout = 1.8v vout = 2.5v conditions v in = 3.3v t jmax = 125 c 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa typical performance curves (continued) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 55 60 65 70 75 80 85 90 95 100 105 maximum output current (a) ambient temperature ( c) output current de - rating vout = 1.0v vout = 1.8v vout = 2.5v vout = 3.3v conditions v in = 5.0v t jmax = 125 c 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa typical performance characteristics vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 5.0v vout = 1.2v iout = 1a vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 5v vout = 3.3v iout = 1a vout (ac coupled) output ripple at 2 0mhz bandwidth conditions vin = 3.3v vout = 1.2v iout = 1a vout (ac coupled) output ripple at 2 0mhz bandwidth conditions vin = 3.3v vout = 1.8v iout = 1a enable enable power up conditions vin = 5.0v vout = 3.3v load = 1a vout enable power down enable conditions vin = 5.0v vout = 3.3v load = 1a vout www.altera.com/enpirion , page 10 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa typical performance characteristics (continued) vout (ac coupled) load transient from 0 to 1a conditions vin = 5v vout = 1.2v load vout (ac coupled) load transient from 0 to 1a conditions vin = 5v vout = 3.3v load vout (ac coupled) load transient from 0 to 1a conditions vin = 3.7v vout = 1.2v load vout (ac coupled) load transient from 0 to 1a conditions vin = 3.3v vout = 1.8v load www.altera.com/enpirion , page 11 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa functional block diagram dac switch vref (+) (-) error amp v sense v fb v out package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp pvin enable pgnd logic compensation network nc(sw) voltage select vs0 vs1 avin vs2 agnd figure 5. functional block diagram www.altera.com/enpirion , page 12 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa functional description functional overview the ep53a8x qa requires only 2 small mlcc capacitors and an 0201mlc resistor for a complete dc - dc converter solution. the device integrates mosfet switches, pwm controller, gate - drive, compensation, and inductor into a tiny 3mm x 3mm x 1.1mm qfn package. advanced package design, along with the high level of integration, provides very low output ripple and noise. the ep53a8x qa uses voltage mode control for high noise immunity and load matching to advanced 90nm loads. a 3 - pin vid allows the user to choose from one of 8 output voltage settings. the ep53a8x qa comes with two vid output voltage ranges. the ep53a8h qa provides v out settings from 1.8v to 3.3v, the ep53a8l qa provides vid settings from 0.8v to 1.5v, and also has an external resistor divider option to program output setting over the 0.6v to v in - 0.5v range. the ep53a8x qa provides the industry?s highest power density of any 1a dcdc converter solution. the key enabler of this revolutionary integration is altera?s proprietary power mosfet technology. the advanced mosfet switches are implemented in deep - submicron cmos to supply very low switching loss at high switching frequencies and to allow a high level of integration. the semiconductor process allows seamless integration of all switching, control, and compensation circuitry. the proprietary magnetics design provides high - density/high- value magnetics in a very small footprint. altera enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. protection features include under - voltage lock - out (uvlo), over - current protection (ocp), short circuit protection, and thermal overload protection. integrated inductor: low - noise low - emi the ep53a8x qa utiliz es a proprietary low loss integrated inductor. the integration of the inductor greatly simplifies the power supply design process. the inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. further, the package layout is optimized to reduce the electrical path length for the high di/dt input ac ripple currents that are a major source of radiated emissions from dc- dc converters. the integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power dcdc converter design. voltage mode control, high bandwidth the ep53a8x qa utilizes an integrated type iii compensation network. voltage mode con trol is inherently impedance matched to the sub 90nm process technology that is used in today?s advanced ics. voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained ove r the entire load range. the very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. soft start internal soft start circuits limit in - rush current when the device starts up from a power down c ondition or when the ?enable? pin is asserted ?high?. digital control circuitry limits the v out ramp rate to levels that are safe for the power mosfets and the integrated inductor. the ep53a8h qa has a soft - start slew rate that is twice that of the ep53a8 l qa . when the ep53a8l qa is configured in external resistor divider mode, the device has a fixed vout ramp time. therefore, the ramp rate will vary with the output voltage setting. output voltage ramp time is given in the electrical characteristics table. excess bulk capacitance on the output of the device can cause an over - current condition at startup. assuming no - load at startup, the www.altera.com/enpirion , page 13 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as: ep53a8l qa : c out_total_max = c out _fi lter + c out _bulk = 250uf ep53a8h qa : c out_total_max = c out _fi lter + c out _bulk = 125uf ep53a8l qa (in external divider mode): c out_total_max = 2.25x10 -4 /v out farads the nominal value for c out is 10uf. see the applications section for more details. over current/short circuit protection the current limit function is achieved by sensing the current flowing through a sense p - mosfet which is compared to a reference current. when this level is exceeded the p - fet is turned off and the n - fet is turned on, pulling v out low. this condition is maintained for approximately 0.5ms and then a normal soft start is initiated. if the over current condition still persists, this cycle will repeat. under volta ge lockout during initial power up, an under voltage lockout circuit will hold - off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. if the lockout circuitry will again disable the switching. hysteres is is included to prevent chattering between states. enable the enable pin provides a means to shut down the converter or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter in to normal operation. not e: the enable pin must not be left floating. thermal shutdown when excessive power is dissipated in the chip, the junction temperature rises. once the junction temperature exceeds the thermal shutdown temperature, the thermal shu tdown circuit turns off the converter output voltage thus allowing the device to cool. when the junction temperature decreases by 25c, the device will go through the normal startup process. www.altera.com/enpirion , page 14 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa application information v out v in 10f 0805 x7r 4.7f 0603 x7r vout pvin avin pgnd agnd vsense EP53A8HQA 100? vs0 vs1 vs2 enable figure 6. ep53a8h qa vid application circuit v out v in 10f 0805 x7r 4.7f 0603 x7r vout pvin avin pgnd agnd vsense ep53a8lqa 100? vfb vs0 vs1 vs2 enable figure 7. ep53a8lqa vid application circuit output voltage programming the ep53a8x qa utilizes a 3 - pin vid to program the output voltage value. the vid is available in two sets of output vid programming ranges. the vid pins should be connected either to an external control signal, avin or to agnd to avoid noise coupling into the device. the ?low? range is optimized for low voltage applications. it comes with preset vid settings ranging from 0.80v and 1.5v. this vid set also has an external divider option. to specify this vid range, order part number ep53a8l qa . the ?high? vid set provides output voltage settings ranging from 1.8v to 3.3v. this version does not have an external divider option. to specify this vid range, order part number ep53a8h qa . internally, the output of the vid multiplexer sets the value for the voltage reference dac, which in turn is connected to the non - inverting input of the error amplifier. this allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. note: the vid pins must not be left floating. table 1 : ep53a8l qa vid voltage select settings ep53a8l low vid range programming the ep53a8l qa is designed to provide a high degree of flexibility in powering applications that require low v out settings and dyn amic voltage scaling (dvs). the device employs a 3- pin vid architecture that allows the user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage divider option. the vid pin settings can be changed on the fly to implement glitch - free voltage scaling. table 1 shows the vs2 - vs0 pin logic states for the ep53a8l qa and the associated output voltage levels. a logic ?1? indicates a connection to avin or to a ?high? logic voltage level. a logic ?0? indicates a connection to agnd or to a ?low? logic voltage level. these pins can be either hardwired to avin or agnd or alternatively can be driven by standard logic levels. log ic levels are defined in the electrical characteristics table. any level between the vs2 vs1 vs0 vout 0 0 0 1.50 0 0 1 1.45 0 1 0 1.20 0 1 1 1.15 1 0 0 1.10 1 0 1 1.05 1 1 0 0.8 1 1 1 ext www.altera.com/enpirion , page 15 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa logic high and logic low is indeterminate. ep53a8l qa external voltage divider the external divider option is chosen by connecting vid pins vs2 - vs0 to v in or a logic ?1? or ?high?. the ep53a8l qa uses a separate feedback pin, v fb , when using the external divider. v sense must be connected to v out as indicated in figure 8 . the output voltage is selected by the following formula: ( ) rb ra out vv += 16.0 v out v in 10f 0805 x7r 4.7f 0603 x7r vout pvin avin pgnd agnd vsense ep53a8lqa 100? vfb vs0 vs1 vs2 enable r a r b figure 8. ep53a8l qa external vout setting r a must be chosen as 237k? to maintain loop gain. then r b is given as: ? ? = 6.0 102.142 3 out b v x r v out can be programmed over the range of 0.6v to (v in ? 0.5v). note: dynamic voltage scaling is not allowed between internal preset voltages and external divider. ep53a8h qa high vid range programming the ep53a8h qa v out settings are optimized for higher nominal voltages such as those required to power io, rf, or ic memory. the preset voltages range from 1.8v to 3.3v. there are eight (8) preset output voltage settings. the ep53a8h qa does not have an external divider option. as with the ep53a8l qa , the vid pin settings can be changed while the device is enabled. table 2 shows the vs0 - vs2 pin logic states for the ep53a8h qa and the associated output voltage levels. a logic ?1? indicates a connection to avin or to a ?high? logic voltage level. a logic ?0? ind icates a connection to agnd or to a ?low? logic voltage level. these pins can be either hardwired to avin or agnd or alternatively can be driven by standard logic levels. logic levels are defined in the electrical characteristics table. any level between the logic high and logic low is indeterminate. these pins must not be left floating. table 2 : ep53a8h qa vid voltage select settings power - up/down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power down, the avin should not be powered down before the pvin. tying pvin and avin or all three pins (avin, pvin, enable) together during power up or power d own meets these requirements . pre - bias start - up the ep53a8x qa does not support startup into a pre - biased condition. be sure the output capacitors are not charged or the output of the ep53a8x qa is not pre - biased when the ep53a8x qa is first enabled. input filter capacitor the input filter capacitor requirement is a 4.7f 0603 low esr mlcc capacitor. the input capacitor must use x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulations lose capacitance with frequency, bias, and wi th temperature, and are vs2 vs1 vs0 vout 0 0 0 3.3 0 0 1 3.0 0 1 0 2.9 0 1 1 2.6 1 0 0 2.5 1 0 1 2.2 1 1 0 2.1 1 1 1 1.8 www.altera.com/enpirion , page 16 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa not suitable for switch - mode dc - dc converter input filter applications. output filter capacitor the output filter capacitor requirement is a minimum of 10f 0805 mlcc. ripple performance can be improved by using 2x10f 0805 mlcc capacitors. the maximum output filter capacitance next to the output pins of the device is 60f low esr mlcc capacitance. v out has to be sensed at the last output filter capacitor next to the ep53a8x qa . additional bulk capacitance for decoupling and bypa ss can be placed at the load as long as there is sufficient separation between the v out sense point and the bulk capacitance. the separation provides an inductance that isolates the control loop from the bulk capacitance. excess total capacitance on the output (output filter + bulk) can cause an over - current condition at startup. refer to the section on soft - start for the maximum total capacitance on the output. the output capacitor must use x7r or equivalent dielectric formulation. y5v or equivalent d ielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch - mode dc - dc converter output filter applications. www.altera.com/enpirion , page 17 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa thermal considerations thermal considerations are important power supply design facts that cannot be avoided in the real world. whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. the enpirion powersoc helps alleviate some of those co ncerns. the enpirion e p53a8 x qa dc- dc converter is packaged in a 3x3x 1.1 mm 16- pin qfn package. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c may reduce long - term reliability. the device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 1 55 c. the following example and calculations illustrate the thermal performance of the ep53a8xqa . example: v in = 5v v out = 3.3v i out = 1a first calculate the output power. p ou t = 3.3v x 1a = 3.3 w next, determine the input power based on the efficiency () shown in figure 9 . figur e 9. efficiency vs. output current for v in = 5v, v ou t = 3.3v at 1a , 86.5 % = p out / p in = 86.5 % = 0.865 p in = p out / p in 3.3 w / 0. 865 3.815w the power dissipation (p d ) is the power loss in the system and can be calculated by subtracting the output power from the input power. p d = p in ? p out 3.815w ? 3.3 w 0.515 w with the power dissipation known, the temperature rise in the device may be estimated based on the theta ja value ( ja ). the ja parameter estimates how much the temperature will rise in the device for every watt of power dissipation. the e p53a8xqa has a ja value of 80 oc/w without airflow. determine the change in temperature (t) based on p d and ja . t = p d x ja t 0.515 w x 80 c/w = 41.2 c 41 c the junction temperature (t j ) of the device is approximately the ambient temperature (t a ) plus the change in temperature. we assume the initial ambient temperature to be 25c. t j = t a + t t j 25c + 41 c 66 c the maximum operating junction temperature (t j max ) of the device is 125c, so the device can operate at a higher ambient temperature. the maximum ambient temperature (t amax ) allowed can be calculated . t amax = t j max ? p d x ja 125c ? 41 c 84 c the maximum ambient temperature (before de - rating) the device can reach is 84 c given the input and output conditions. note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. 35 40 45 50 55 60 65 70 75 80 85 90 95 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 efficiency (%) output current (a) efficiency vs. i out (v in = 5.0v) vout = 3.3v odto v = 5v 8.5 .. 18 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa layout recommendations figure 10 shows critical components and layer 1 traces of a recommended minimum footprint ep53a8l qa /ep53a8h qa layout with enable tied to v in . alternate enable configurations, and other small signal pins need to be connected and routed according to specific customer application. please see the gerber files on the altera website www.altera.com/enpirion for exact dimensions and other layers. please refer to figure 10 while reading the layout recommendations in this section. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the ep53a8 xqa package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the c apacitors and the ep53a8 xqa should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: input and output grounds are separated until they connect at the pgnd pins. the separa tion shown on figure 10 between the input and output gnd circuits helps minimize noise coupling between the converter input and output switching loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and the input/output capacitors. please see the gerber files on the altera website www. altera.com/enpirion . figure 10. top pcb layer critical components and copper for minimum footprint recommendation 4 : multiple small vias should be used to connect the ground traces under the device to the system ground plane on another layer for h eat dissipation. the drill diameter of the vias should be 0.33mm , and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20 - 0.26mm . do not use thermal reliefs or spokes to connect the vias to the gro und plane. it is preferred to put these vias under the capacitors along the edge of the gnd copper closest to the +v copper. please see figure 10. these vias connect the input/output filter capacitors to the gnd plane and help reduce parasitic inductances in the input and output current loops. if the vias cannot be placed under c in and c out , then put them just outside the capacitors along the gnd. do not use thermal reliefs or spokes to connect these vias to the ground plane. recommendation 5 : avin is the p ower supply for the internal small - signal control circuits. it should be connected to the input voltage at a quiet point. in figure 10 this connection is made with ravin at the input capacitor close to the v in connection. www.altera.com/enpirion , page 19 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa recommended pcb footprint figur e 11. e p53a8x qa pcb footprin t ( top view) www.altera.com/enpirion , page 20 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa package and mechanical figur e 12. e p53a8 l qa package dimensions (bottom view) www.altera.com/enpirion , page 21 10366 october 1, 2014 rev a
ep53a8l qa /ep53a8h qa figure 13. EP53A8HQA package dimensions (bottom view) packing and marking information : www.altera.com/support/reliability/packing/rel - packing - and- marking.html contact information altera corporation 101 inno vation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 201 4 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or s erv ices. www.altera.com/enpirion , page 22 10366 october 1, 2014 rev a

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